Keysight Technologies D9020DDRC, Manual

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16 Data Timing Tests
272 DDR2(+LP) Compliance Testing Methods of Implementation
tDH(derate), Differential DQ and DM Input Hold Time with Derating Support - Test Method of
Implementation
The purpose of this test is to verify that the time interval from the data or data mask (DQ/DM
rising/falling edge) hold time to the associated DQS crossing edge is within the conformance limits
as specified in the JEDEC specification.
Signals of Interest
Mode Supported: DDR2, LPDDR2
Signal cycle of interest: WRITE
Signal(s) of Interest:
• Data Signal (supported by Data Strobe Signal)
• Data Mask Signal
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQ signals from different rank of memory)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ or Data Mask Signal, DM
• Data Strobe Signal, DQS (this must use a differential DQS connection)
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Table 186 Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) & (DDR2-667 and DDR2-800)
Parameter Symbol DDR2-400 DDR2-533 Units Specific Notes
Min Max Min Max
DQ and DM input hold time (differential strobe) tDH(base) 275 x 225 x ps 6,7,8,21,28
Parameter Symbol DDR2-667 DDR2-800 Units Specific Notes
Min Max Min Max
DQ and DM input hold time tDS(base) 175 x 125 x ps 6,7,8,21,28,31
Table 187 DDR2-400/533 tDS/tDH derating with differential data strobe
∆
tDS,
∆
tDH derating values for DDR2-400, DDR2-533 (All units in ‘ps’; the note applies to the entire table.)
DQS, DQS Differential Slew Rate
4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns
∆
tDS
∆
tDH
∆
tDS
∆
tDH
∆
tDS
∆
tDH
∆
tDS
∆
tDH
DQ Slew Rate V/ns 2.0 125 45 125 45 125 45 - -
1.5 83 21 83 21 83 21 95 33
1.0 0 0 0 0 0 0 12 12
0.9 - - -11 -14 -11 -14 1 -2
0.8 - - - - -25 -31 -13 -19