Keysight Technologies D9020DDRC, Manual

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3 Measurement Clock Tests
34 DDR2(+LP) Compliance Testing Methods of Implementation
Clock Period Jitter - tJIT(per) - Test Method of Implementation
This test is applicable to the Rising Edge Measurement and Falling Edge Measurement. The purpose
of this test is to measure the difference between a measured clock period and the average clock
period across multiple cycles of the clock. You can specify the rising and/or the falling edge of your
signal for this measurement.
Signals of Interest
Mode Supported: DDR2, LPDDR2
Signal cycle of interest: READ or WRITE
Signal(s) of Interest:
• Clock Signal
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - any signal of interest, as defined above
Test Definition Notes from the Specification
Test References
See Specific Note 35 in the JEDEC Standard JESD79-2E and Specific Note 30 in the JESD208 , and
Table 103 in the JESD209-2B.
Table 2 Specific Note 35
Parameter Symbol DDR2-667 DDR2-800 Units Notes
Min Max Min Max
Clock Period Jitter tJIT(per) -125 125 -100 100 ps 35
Table 3 Specific Note 30
Parameter Symbol DDR2-1066 Units Notes
Min Max
Clock Period Jitter tJIT(per) -90 90 ps 30
Table 4 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Max.
Frequency
*4
533 466 400 333 266 233 200 166 133 100 MHz
Clock Timing
Clock Period
Jitter (with
allowed jitter)
t
JIT
(per),
allowed
Min -90 -95 -100 -110 -120 -130 -140 -150 -180 -250
ps
Max 90 95 100 110 120 130 140 150 180 250