Keysight Technologies D9020DDRC, Manual

Page: 257 / 370

DDR2(+LP) Compliance Testing Methods of Implementation 241
Data Strobe Timing (DST) Tests 15
Measurement Algorithm
1 Acquire and split read and write burst of the acquired signal.
2 Take the first valid READ burst found.
3 Find Data tHZEndPoint of the said burst.
4 Find RL Clock edge (tDQSCK clock edge reference).
• Find all DQS rising middle crossing points in the burst.
• Find the first DQS rising edge by searching for the earliest rising crossing point in all of the
found DQS middle crossing points.
• Find the closest Clock-DQS (the Clock middle crossing point that is closest to the first DQS
rising edge).
• Find the RL Clock edge (tDQSCK clock edge reference) which is the Clock middle crossing
point immediately before the closest Clock-DQS to tDQSCK Delay (cycle). By default, tDQSCK
Delay is one cycle. For example, if tDQSCK Delay = 1 then the tDQSCK Clock point is the Clock
middle crossing point that is prior to the closest Clock-DQS. If tDQSCK Delay = 3 then the
tDQSCK Clock point is the Clock middle crossing point three clock cycles before the closest
Clock-DQS. tDQSCK Delay is configurable in the configuration page.
5 Define BL (bit length) to be the number of DQS middle crossing points.
6 Find “RL+BL/2” Clock edge (Clock rising middle crossing point that is BL/2 cycles after the RL
Clock edge.
7 Compare the Data tHZ end point to the “RL+BL/2” Clock edge as the test result.
Mathematically, the test result = Data tHZ end point - “RL+BL/2” Clock edge point.
8 Display the test result by going to the measurement location on the waveform and locate the
marker to Data tHZ end point and Clock middle cross point of the test result.
9 Compare the test result against the compliance test limit.
NOTE
Some designs do not have tri-state at V
REF
(for example, 0.9V). This test is not guaranteed when
this scenario happens, as there is no significant point of where the driver has been turned-off.