Keysight Technologies D9020DDRC, Manual

Page: 7 / 370

DDR2(+LP) Compliance Testing Methods of Implementation 7
In This Book
This manual describes the tests that are performed by the DDR2(+LP) Compliance Test Application in
more detail; it contains information from (and refers to) the
JESD79-2E and JESD208, and it
describes how the tests are performed.
•
Chapter 1 , “Installing the DDR2(+LP) Compliance Test Application"” shows how to install and
license the automated test application software (if it was purchased separately).
• Chapter 2 , “Preparing to Take Measurements" shows how to start the DDR2(+LP) Compliance
Test Application and gives a brief overview of how it is used.
• Chapter 3 , “Measurement Clock Tests" describes the measurement clock tests including clock
period jitter, clock to clock period jitter, cumulative error, average HIGH and LOW pulse width,
half period jitter and average clock period tests.
• Chapter 4 , “Single-Ended Signals AC Input Parameters Tests" shows how to run the
single-ended signals AC input parameters tests. This chapter includes input signal maximum
peak to peak swing tests, input signal minimum slew rate (rising) tests, input signal minimum
slew rate (falling) tests, input logic HIGH tests and input logic LOW tests.
• Chapter 5 , “Single-Ended Signals VIH/VIL (Address, Control) Tests" describes the AC/DC input
logic high/low tests (address, control).
• Chapter 6 , “Single-Ended Signals VIH/VIL (Data, Mask) Tests" describes the AC/DC input logic
high/low tests (data, mask).
• Chapter 7 , “Single-Ended Signals AC Parameters Tests for Strobe Signals" describes the V
SEH(AC)
and V
SEL(AC)
tests for strobe signals.
• Chapter 8 , “Single-Ended Signals AC Parameters Tests for Clock" describes the V
SEH(AC)
and
V
SEL(AC)
tests for clocks.
• Chapter 9 , “Single-Ended Signals Overshoot/Undershoot Tests" describes the AC overshoot and
undershoot tests probing and method of implementation.
• Chapter 10 , “Differential Signals AC Input Parameters Tests" describes the V
ID
AC differential
input voltage tests and V
IX
AC differential cross point voltage tests. The V
IHdiff
and V
ILdiff
tests for
both AC and DC are also described.
• Chapter 11 , “Differential Signal AC Output Parameters Tests" contains information on the V
OX
AC
differential cross point voltage tests. It also describes the SRQdiffR (40 and 60 ohm), SQRdiffF
(40 and 60 ohm), V
OHdiff(AC)
, and V
OLdiff(AC)
tests.
• Chapter 12 , “Differential Signal Clock Cross Point Voltage Tests" describes the V
IXCA
Clock Cross
Point Voltage test.
• Chapter 13 , “Differential Signals Strobe Cross Point Voltage Tests" describes the V
IXDQ
Strobe
Cross Point Voltage test.
• Chapter 14 , “Clock Timing (CT) Tests" describes the clock timing operating conditions of
DDR2/LPDDR2 SDRAM as defined in the specification.
• Chapter 15 , “Data Strobe Timing (DST) Tests" describes various data strobe timing tests
including tHZ(DQ), tLZ(DQS), tLZ(DQ), tDQSQ, tQH, tDQSS, tDQSH, tDQSL, tDSS, tDSH, tWPST,
tWPRE, tRPRE, tRPST, tHZ(DQ) Low Power, tHZ(DQS) Low Power, tLZ(DQS) Low Power, tLZ(DQ)
Low Power, tQSH, tQSL, tDQSS, and tDVAC (Strobe) tests.
• Chapter 16 , “Data Timing Tests" describes the measurement clock tests including clock period
jitter, clock to clock period jitter, cumulative error, average HIGH and LOW pulse width, half
period jitter and average clock period tests.
• Chapter 17 , “Command and Address Timing (CAT) Tests" describes the measurement clock tests
including clock period jitter, clock to clock period jitter, cumulative error, average HIGH and LOW
pulse width, half period jitter and average clock period tests.
• Chapter 18 , “Custom Mode Read-Write Eye-Diagram Tests" describes the user defined real-
time eye- diagram test for read cycle and write cycle.
• Chapter 19 , “Calibrating the Infiniium Oscilloscope and Probe" describes how to calibrate the
oscilloscope in preparation for running the DDR2(+LP) automated tests.