Keysight Technologies D9020DDRC, Manual

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4 Single-Ended Signals AC Input Parameters Tests
66 DDR2(+LP) Compliance Testing Methods of Implementation
V
IH(DC)
Test for DQS - Test Method of Implementation
V
IH(DC)
- Minimum DC Input Logic HIGH for DQS.
The purpose of this test is to verify that the high level voltage value of the test signal within a valid
sampling window is greater than the conformance lower limits of the V
IH(DC)
value specified in the
JEDEC specification.
The value of V
REF
which directly affects the conformance lower limit is set to 0.9V. User may choose
to use the UDL (User Defined Limit) feature in the application to perform this test against a
customized test limit set based on the different values of V
REF
.
The value of V
DDQ
which directly affects the conformance upper limit is set to 1.8V. User may choose
to use the UDL (User Defined Limit) feature in the application to perform this test against a
customized test limit set based on the different values of V
DDQ
.
Signals of Interest
Mode Supported: DDR2 only
Signal cycle of interest: WRITE
Required Read/Write separation: Yes
Signal(s) of Interest:
• Data Strobe Signals (supported by Data Signals)
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - Data Strobe Signals
• Supporting Pin - Data Signals
Test Definition Notes from the Specification
Test References
See Table 19 - Input DC Logic Level, in the JEDEC Standard JESD79-2E and Table 19 - Input DC
Logic Level in the JESD208 .
Table 35 Input DC Logic Level
Symbol Parameter Min Max Units Notes
V
IH(DC)
DC input logic HIGH V
REF
+ 0.125 V
DDQ
+ 0.3 V -
Table 36 Input DC Logic Level (DDR2-1066)
Symbol Parameter Min Max Units Notes
V
IH(DC)
DC input logic HIGH V
REF
+ 0.125 V
DDQ
+ 0.3 V -