Keysight Technologies D9020DDRC, Manual

Page: 163 / 370

DDR2(+LP) Compliance Testing Methods of Implementation 147
Differential Signals AC Input Parameters Tests 10
Test References
See Table 22 - Differential Input AC Logic Level in the JEDEC Standard JESD79-2E and Table 22 -
Differential Input AC Logic Level in the JESD208 .
PASS Condition
The calculated magnitude of the differential voltage of the test signals pair should be within the
conformance limits of the V
ID(AC)
value.
Measurement Algorithm
1 Sample/acquire data waveforms.
2 Use Subtract FUNC to generate the differential waveform from the two source inputs.
3 Split read and write burst of the acquired signal.
4 Take the first valid WRITE burst found.
5 Find all differential DQS crossing that cross 0V.
6 Within the first and second DQS crossing regions, perform V
TOP
on DQS,Gnd or /DQS,Gnd
depending on which one is the positive pulse in current region. Next, perform V
BASE
on DQS,Gnd
or /DQS,Gnd depending on which one is the negative pulse in the current region. Calculate
V
ID(AC)
= V
TOP
- V
BASE
.
7 Perform the previous step on all pairs of DQS crossing.
8 Determine the worst result from the set of V
ID(AC)
measured.