Keysight Technologies D9020DDRC, Manual

Page: 210 / 370

14 Clock Timing (CT) Tests
194 DDR2(+LP) Compliance Testing Methods of Implementation
tAC, DQ Output Access Time from CK/CK# - Test Method of Implementation
The purpose of this test is to verify that the time interval from data output (DQ rising and falling edge)
access time to the nearest rising or falling edge of the clock must be within the conformance limit as
specified in the JEDEC specification.
Signals of Interest
Signal cycle of interest: READ
Mode Supported: DDR2
Signal(s) of Interest:
• Data Signal (supported by Data Strobe Signal)
• Clock Signal (CK as Reference Signal)
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQ signals from different rank of memory.)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ
• Data Strobe Signal, DQS
• Clock Signal, CK
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Test References
See Table 41 - Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) and Table 42 -
Timing Parameters by Speed Grade (DDR2-667 and DDR2-800) in the
JEDEC Standard JESD79-2E .
Also see Table 41 - Timing Parameters by Speed Grade (DDR2-1066) in the JESD208 .
Table 117 Timing Parameters by Speed Grade (DDR2-400 and DDR-533) & (DDR2-667 and DDR2-800)
Parameter Symbol DDR2-400 DDR2-533 Units Specific Notes
Min Max Min Max
DQ output access time from CK/CK tAC -600 +600 -500 +500 ps
Parameter Symbol DDR2-667 DDR2-800 Units Specific Notes
Min Max Min Max
DQ output access time from CK/CK tAC -450 450 -400 400 ps 40
Table 118 Timing Parameters by Speed Grade (DDR2-1066)
Parameter Symbol DDR2-1066 Units Specific Notes
Min Max
DQ output access time from CK/CK tAC -350 350 ps 35