4
Single-Ended Signals AC Input Parameters Tests
62
DDR2(+LP) Compliance Testing Methods of Implementation
V
IH(AC)
Test for Address, Control - Test Method of Implementation
V
IH(AC)
- Maximum AC Input Logic HIGH for Address, Control.
The purpose of this test is to verify that the mode of histogram of the high level voltage value of the
test signal within a valid sampling window is greater than the conformance lower limits of the V
IH(AC)
value specified in the JEDEC specification.
The value of V
REF
which directly affects the conformance lower limit is set to 0.9V. User may choose
to use the UDL (User Defined Limit) feature in the application to perform this test against a
customized test limit set based on the different values of V
REF
.
The value of V
PEAK
which directly affects the conformance upper limit is set to 0.5V. User may choose
to use the UDL (User Defined Limit) feature in the application to perform this test against a
customized test limit set based on the different values of V
PEAK
.
The value of V
DDQ
which directly affects the conformance upper limit is set to 1.8V. User may choose
to use the UDL (User Defined Limit) feature in the application to perform this test against a
customized test limit set based on the different values of V
DDQ
.
Signals of Interest
Mode Supported: DDR2 only
Signal cycle of interest: WRITE
Required Read/Write separation: No
Signal(s) of Interest:
• Address Signals OR
• Control Signals OR
• Clock Signals
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - any of the signal of interest defined above.
Test Definition Notes from the Specification
Test References
See Table 20 - Input AC Logic Level in the
JEDEC Standard JESD79-2E
and Table 20 - Input AC
Logic Level in the
JESD208
.
Table 31
Input AC Logic Level
Symbol
Parameter
DDR2-400, DDR2-533
DDR2-667, DDR2-800
Units
Notes
Min
Max
Min
Max
V
IH(AC)
AC input logic HIGH
V
REF
+ 0.250
V
DDQ
+V
PEAK
V
REF
+ 0.200
V
DDQ
+V
PEAK
V
1
Table 32
Input AC Logic Level (DDR2-1066)
Symbol
Parameter
DDR2-1066
Units
Notes
Min
Max
V
IH(AC)
AC input logic HIGH
V
REF
+ 0.200
-
V
-
Summary of Contents for D9020DDRC
Page 1: ...Keysight D9020DDRC DDR2 LP Compliance Test Application Methods of Implementation ...
Page 10: ...10 DDR2 LP Compliance Testing Methods of Implementation ...
Page 46: ...2 Preparing to Take Measurements 30 DDR2 LP Compliance Testing Methods of Implementation ...
Page 70: ...3 Measurement Clock Tests 54 DDR2 LP Compliance Testing Methods of Implementation ...
Page 224: ...14 Clock Timing CT Tests 208 DDR2 LP Compliance Testing Methods of Implementation ...
Page 270: ...15 Data Strobe Timing DST Tests 254 DDR2 LP Compliance Testing Methods of Implementation ...