Keysight Technologies D9020DDRC, Manual

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15 Data Strobe Timing (DST) Tests
222 DDR2(+LP) Compliance Testing Methods of Implementation
tDQSS, DQS Latching Transition to Associated Clock Edge - Test Method of Implementation
The purpose of this test is to verify that the time interval from the data strobe output (DQS falling
edge) access time to the associated clock (crossing point) is within the conformance limit as
specified in the JEDEC specification.
Signals of Interest
Mode Supported: DDR2, for LPDDR2 refer to the tDQSS Test (Low Power)
Signal cycle of interest: Write
Signal(s) of Interest:
• Data Strobe Signal (supported by Data Signal)
• Clock Signal
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQ signals from different rank of memory.)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ
• Data Strobe Signal, DQS
• Clock Signal, CK
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Test References
See Table 41 - Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) and Table 42 -
Timing Parameters by Speed Grade (DDR2-667 and DDR2-800), in the
JEDEC Standard JESD79-2E .
Also see Table 41 - Timing Parameters by Speed Grade (DDR2-1066) in the JESD208 .
Table 138 Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) & (DDR2-667 and DDR2-800)
Parameter Symbol DDR2-400 DDR2-533 Units Specific
Notes
Min Max Min Max
DQS latching rising transitions to associated clock edges tDQSS -0.25 0.25 -0.25 0.25 tCK
Parameter Symbol DDR2-667 DDR2-180 Units Specific
Notes
Min Max Min Max
DQS latching rising transitions to associated clock edges tDQSS -0.25 0.25 -0.25 0.25 tCK(avg) 30
Table 139 Timing Parameters by Speed Grade (DDR2-1066)
Parameter Symbol DDR2-1066 Units Specific
Notes
Min Max
DQS latching rising transitions to associated clock edges tDQSS -0.25 0.25 tCK(avg) 25