Keysight Technologies D9020DDRC, Manual

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DDR2(+LP) Compliance Testing Methods of Implementation 291
Data Timing Tests 16
tDIPW, DQ and DM Input Pulse Width - Test Method of Implementation
The purpose of this test is to verify that the width of the high or low level of the Data signal is within
the conformance limit as specified in the JEDEC specification.
Signals of Interest
Mode Supported: LPDDR2 only
Signal cycle of interest: WRITE
Signal(s) of Interest:
• Data Signal (supported by Data Strobe Signal)
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQS signals from different rank of memory)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ
• Data Strobe Signal, DQS
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Test References
See Table 103 - LPDDR2 AC Timing Table in the JEDEC Standard JESD209-2B .
PASS Condition
The worst measured tDIPW should be within the specification limit.
Measurement Algorithm
1 Acquire and split read and write burst of the acquired signal.
2 Take the first valid WRITE burst found.
3 Find all of the valid rising and falling DQ crossings at V
REF
in this burst.
4 tDIPW is the time interval starting from a rising/falling edge of the DQ and ending at the
following falling/rising edge (the following edge should be in the opposite direction).
5 Collect all tDIPW.
6 Determine the worst result from the measured tDIPW.
Table 201 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Write Parameters*
14
DQ and DM
input pulse
width
tDIPW Min
0.35 t
CK(avg)