Keysight Technologies D9020DDRC, Manual

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15 Data Strobe Timing (DST) Tests
228 DDR2(+LP) Compliance Testing Methods of Implementation
tDSS, DQS Falling Edge to CK Setup Time - Test Method of Implementation
The purpose of this test is to verify that the time interval from the falling edge of the data strobe (DQS
falling edge) output access time to the clock setup time, is within the conformance limit as specified
in the JEDEC specification.
Signals of Interest
Mode Supported: DDR2, LPDDR2
Signal cycle of interest: WRITE
Signal(s) of Interest:
• Data Strobe Signal (supported by Data Signal)
• Clock Signal
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQ signals from different rank of memory)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ
• Data Strobe Signal, DQS
• Clock Signal, CK
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Table 146 Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) & (DDR2-667 and DDR2-800)
Parameter Symbol DDR2-400 DDR2-533 Units Specific
Notes
Min Max Min Max
DQS falling edge to CK setup time tDSS 0.2 x 0.2 x tCK(avg)
Parameter Symbol DDR2-667 DDR2-800 Units Specific
Notes
Min Max Min Max
DQS falling edge to CK setup time tDSS 0.2 x 0.2 x tCK(avg) 30
Table 147 Timing Parameters by Speed Grade (DDR2-1066)
Parameter Symbol DDR2-1066 Units Specific
Notes
Min Max
DQS falling edge to CK setup time tDSS 0.2 x tCK(avg) 25
Table 148 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Write Parameters*
14
DQS falling edge
to CK setup time
tDSS Min
0.2 tCK(avg)