Keysight Technologies D9020DDRC, Manual

Page: 57 / 370

DDR2(+LP) Compliance Testing Methods of Implementation 41
Measurement Clock Tests 3
Cumulative Error (across 13-50 cycles) - tERR (13-50 per) (Low Power) - Test Method of Im -
plementation
This Cumulative Error (across 13- 50 cycles) test is applicable to the Rising Edge Measurement as
well as the Falling Edge Measurement. The purpose of this test is to measure the difference between
a measured clock period and the average clock period across multiple cycles of the clock from 13
cycles to 50 cycles.
Signals of Interest
Mode Supported: LPDDR2 only
Signal cycle of interest: READ or WRITE
Signal(s) of Interest:
• Clock Signal
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - any signal of interest, as defined above
Test Definition Notes from the Specification
Test References
See Table 103 in the JEDEC Standard JESD209-2B .
Pass Condition
The tERR measurement value from 13- cycle through 50 cycle should be within the conformance
limits as specified in the JEDEC specification.
Measurement Algorithm
Example input test signal: Frequency: 1 KHz, Number of cycles acquired: 202. tERR(13- 50per)
executes tERR(13per) through tERR(50per). For tERR(13per):
1 Calculate the average for periods 1-200.
2 Calculate the average for periods 1-13.
3 Measure the difference between these two averages and save the answer as a tERR(13per)
result.
Table 11 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Max.
Frequency
*4
533 466 400 333 266 233 200 166 133 100 MHz
Clock Timing
Cumulative
error across n =
13, 14, ... 49,
50 cycles
t
ERR
(nper),
allowed
Min t
ERR
(nper), allowed, min = {1 + 0.68ln(n)} * t
JIT
(per), allowed, min
ps
Max t
ERR
(nper), allowed, max = {1 + 0.68ln(n)} * t
JIT
(per), allowed, max