Keysight Technologies D9020DDRC, Manual

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15 Data Strobe Timing (DST) Tests
236 DDR2(+LP) Compliance Testing Methods of Implementation
tRPRE, Read Preamble - Test Method of Implementation
The purpose of this test is to verify that the time when the DQS start driving LOW (*preamble
behavior) to the first DQS signal crossing for the Read cycle must be within the conformance limit as
specified in the JEDEC specification.
Signals of Interest
Mode Supported: DDR2, LPDDR2
Signal cycle of interest: READ
Signal(s) of Interest:
• Data Strobe Signal (supported by Data Signal)
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQ signals from different rank of memory)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ
• Data Strobe Signal, DQS
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Table 158 Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) & (DDR2-667 and DDR2-800)
Parameter Symbol DDR2-400 DDR2-533 Units Specific
Notes
Min Max Min Max
READ Preamble tRPRE 0.9 1.1 0.9 1.1 tCK 19
Parameter Symbol DDR2-667 DDR2-800 Units Specific
Notes
Min Max Min Max
READ Preamble tRPRE 0.9 1.1 0.9 1.1 tCK(avg) 19, 41
Table 159 Timing Parameters by Speed Grade (DDR2-1066)
Parameter Symbol DDR2-1066 Units Specific
Notes
Min Max
READ Preamble tRPRE 0.9 1.1 tCK(avg) 16,36
Table 160 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Read Parameters*
14
READ Preamble tRPRE Min 0.9 tCK(avg)