Keysight Technologies D9020DDRC, Manual

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14 Clock Timing (CT) Tests
202 DDR2(+LP) Compliance Testing Methods of Implementation
tQHS, Data Hold Skew Factor- Test Method of Implementation
The purpose of this test is to verify that the time interval from the data output (DQ rising and falling
edge) associated with a falling clock edge access time to the nearest falling edge of the clock must
be within the conformance limits as specified in the JEDEC specification.
Signals of Interest
Signal cycle of interest: READ
Mode Supported: LPDDR2
Signal(s) of Interest:
• Data Signals (supported by Data Strobe Signal)
• Clock Signal (CK as Reference Signal)
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQS signals from different rank of memory.)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ
• Data Strobe Signal, DQS
• Clock Signal, CK
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Test References
See Table 103- LPDDR2 AC Timing Table in the JESD209-2B .
PASS Condition
The worst measured tQHS should be within the specification limit.
Table 123 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Read Parameters*
14
Data hold skew
factor
tQHS Max
230 260 280 340 400 450 480 600 750 1000 ps