Keysight Technologies D9020DDRC, Manual

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17 Command and Address Timing (CAT) Tests
310 DDR2(+LP) Compliance Testing Methods of Implementation
See Table 41 - Timing Parameters by Speed Grade (DDR2- 1066) and Table 43 - Derating Values for
DDR2- 1066 in thee
JESD208 .
Also see Table 104 - CA and CS_n Setup and Hold Base-Values for 1V/ns, Table 105 - Derating
Values LPDDR2 tIS/tIH - AC/DC Based AC220 and Table 106 - Derating Values LPDDR2 tIS/tIH -
AC/DC Based AC300 in the
JESD209-2B .
PASS Condition
The measured time interval between the address/control setup time and the respective clock
crossing point should be within the specification limit.
Measurement Algorithm
1 Pre-condition the oscilloscope.
2 Trigger on either rising or falling edge of the address/control signal under test.
3 Find all crossings on rising edge of the signal under test that cross V
IH(AC)
.
4 Find all crossings on falling edge of the signal under test that cross V
IL(AC)
.
5 For all the crossings found, locate the nearest Clock crossings that cross 0V.
Note: For LPDDR2 with PUT=CA option, the Clock crossing could be Clock rising or Clock falling.
For other cases, the Clock crossing must be Clock rising only.
6 Take the time different of the signal under test's crossings to the corresponding clock crossing as
tIS.
7 Collect all measured tIS.
8 Report the worst tIS measured as test result.
9 Measure the mean slew rate for all the ADD/CMD and CK edges.
10 Use the mean slew rate for ADD/CMD and CK to determine the ∆tIS derating value based on the
derating tables.
11 The test limit for tIS test = tIS(base) + ∆tIS.