Keysight Technologies D9020DDRC, Manual

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15 Data Strobe Timing (DST) Tests
250 DDR2(+LP) Compliance Testing Methods of Implementation
tDQSS Test (Low Power), DQS Latching Transition to Associated Clock Edge - Test Method of
Implementation
The purpose of this test is to verify that the time interval from the data strobe output (first DQS rising
edge) access time to the reference clock which is before the associated clock (crossing point) is
within the conformance limit as specified in the JEDEC specification.
Signals of Interest
Mode Supported: LPDDR2, for DDR2 refer to the tDQSS Test
Signal cycle of interest: Write
Signal(s) of Interest:
• Data Strobe Signal (supported by Data Signal)
• Clock Signal
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQ signals from different rank of memory)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ
• Data Strobe Signal, DQS
• Clock Signal, CK
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Test References
See Table 103 - LPDDR2 AC Timing Table in the JESD209-2B .
PASS Condition
The measured tDQSS shall be within the specification limit.
Table 170 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Write Parameters*
14
Write command
to first DQS
latching
transition
tDQSS
Min 0.75
t
CK
(avg)
Max
1.25