Keysight Technologies D9020DDRC, Manual

Page: 215 / 370

DDR2(+LP) Compliance Testing Methods of Implementation 199
Clock Timing (CT) Tests 14
Measurement Algorithm
1 Acquire and split read and write burst of the acquired signal.
2 Take the first valid READ burst found.
3 Find all DQS middle cross points at V
REF
in the burst.
4 Find all Clock middle cross points at V
REF
in the burst.
5 Find the first DQS rising edge in the READ burst by searching for the earliest rising cross point
among all the DQS middle cross points. Take the first DQS rising edge as the tDQSCK strobe
point.
6 Find the closest Clock-DQS (the Clock rising middle crossing point that is closest to the first DQS
rising edge).
7 Find the tDQSCK clock point. It is the Clock middle crossing point right before the closest
Clock-DQS at tDQSCK Delay (cycle). By default, tDQSCK Delay is one cycle. For example, if
tDQSCK Delay = 1, then the tDQSCK clock point is the Clock middle crossing point right before
the closest Clock-DQS. If tDQSCK Delay = 3, then the tDQSCK clock point is the Clock middle
crossing point three clock cycles before the closest Clock-DQS. tDQSCK Delay is configurable in
the configuration page.
8 Compare the tDQSCK strobe point to the tDQSCK clock point as the test result. Mathematically,
test result = tDQSCK strobe point - tDQSCK clock point.
9 Display the test result by going to the measurement location on the waveform and locate the
marker to tDQSCK strobe point and tDQSCK clock point.
10 Compare the test result against the compliance test limit.