DDR2(+LP) Compliance Testing Methods of Implementation
165
Differential Signals AC Input Parameters Tests
10
Measurement Algorithm
1 Pre-condition the oscilloscope.
2 Triggered on a rising edge of the clock signal under test.
3 Find all valid Clock negative pulses in the triggered waveform. A valid Clock negative pulse starts
at the 0V crossing on a valid Clock falling edge (see notes on threshold) and ends at the 0V
crossing on the following valid Clock rising edge (see notes on threshold).
4 For the first valid Clock negative pulse, zoom in on the pulse so that it appears on the
oscilloscope’s display, and perform the V
BASE
measurement. Take the V
BASE
measurement result
as the V
ILdiff(AC)
value.
5 Continue the previous step for the rest of the valid Clock negative pulses.
6 Determine the worst result from the set of V
ILdiff(AC)
measured.
Summary of Contents for D9020DDRC
Page 1: ...Keysight D9020DDRC DDR2 LP Compliance Test Application Methods of Implementation ...
Page 10: ...10 DDR2 LP Compliance Testing Methods of Implementation ...
Page 46: ...2 Preparing to Take Measurements 30 DDR2 LP Compliance Testing Methods of Implementation ...
Page 70: ...3 Measurement Clock Tests 54 DDR2 LP Compliance Testing Methods of Implementation ...
Page 224: ...14 Clock Timing CT Tests 208 DDR2 LP Compliance Testing Methods of Implementation ...
Page 270: ...15 Data Strobe Timing DST Tests 254 DDR2 LP Compliance Testing Methods of Implementation ...
