Keysight Technologies D9020DDRC, Manual

Page: 262 / 370

15 Data Strobe Timing (DST) Tests
246 DDR2(+LP) Compliance Testing Methods of Implementation
tLZ(DQ) Test (Low Power), DQ Low Impedance Time From Clock - Test Method of Implemen -
tation
The purpose of this test is to verify that the time when the DQ starts driving (from high impedance
state to HIGH/LOW state), to the reference clock signal crossing, is within the conformance limit as
specified in the JEDEC specification.
Signals of Interest
Mode Supported: LPDDR2, for DDR2 refer to tLZ(DQ) Test
Signal cycle of interest: READ
Signal(s) of Interest:
• Data Signal (supported by Data Strobe Signal)
• Clock Signal (CK as Reference Signal)
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQ signals from different rank of memory)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ
• Data Strobe Signal, DQS
• Clock Signal, CK
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Test References
See Table 103 - LPDDR2 AC Timing Table in the JESD209-2B .
PASS Condition
The measured tLZ(DQ) shall be within the specification limit.
Table 167 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Read Parameters*
14
DQ low-Z from
clock
*15
tLZ(DQ) Min
t
DQSCK
(min) + {1.4 * t
QHS
(max)} ps