8
Single-Ended Signals AC parameter tests for Clocks
130
DDR2(+LP) Compliance Testing Methods of Implementation
V
SEL(AC)
(clock) - Test Method of Implementation
V
SEL(AC)
- Single- ended Low Level Voltage.
The purpose of this test is to verify that the minimum low pulse voltage must be within the
conformance limit of the V
SEL(AC)
value as specified in the JEDEC specification.
The value of V
DDCA
(which directly affects the conformance limit) is set to 1.2V for the compliance
limit set used. You may choose to use the User Defined Limit feature in the application to perform
this test against a customized test limit set based on different values of V
DDCA
.
Signals of Interest
Mode Supported: LPDDR2 only
Signal cycle of interest: WRITE
Signal(s) of Interest:
• Clock Signals
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - Clock Signals
Test Definition Notes from the Specification
Test References
See Table 79 - Single-ended Levels for CK_t, DQS_t, CK_c, and DQS_c in the
JESD209-2B
.
PASS Condition
The worst measured V
SEL(AC)
shall be within the specification limit.
Measurement Algorithm
1 Pre-condition the oscilloscope.
2 Trigger on a rising edge of the clock signal under test.
3 Find all valid Clock negative pulses in the entire waveform. A valid Clock negative pulse starts at
the V
REF
crossing on a valid Clock falling edge and ends at the V
REF
crossing on the following
valid Clock rising edge.
4 For the first valid Clock negative pulse, zoom in on the pulse so that it appears on the
oscilloscope’s display and perform T
MIN
. Then perform V
TIME
at the found T
MIN
to get the
minimum voltage of the pulse. Take the V
TIME
measurement result as the V
SEL(AC)
value.
5 Continue the previous step for the rest of the valid Clock negative pulses that were found in the
waveform.
6 Determine the worst result from the set of V
SEL(AC)
measured.
Table 78
LPDDR2 Single-ended Levels for CK_t, DQS_t, CK_c, and DQS_c
Symbol
Parameter
LPDDR2-1066 to LPDDR2-466
LPDDR2-400 to LPDDR2-200
Units
Notes
Min
Max
Min
Max
V
SEL(AC)
Single-ended low level for CK_t, CK_c
Note 3
(V
DDCA
/2) - 0.220
Note 3
(V
DDCA
/2) - 0.300
V
1, 2
Summary of Contents for D9020DDRC
Page 1: ...Keysight D9020DDRC DDR2 LP Compliance Test Application Methods of Implementation ...
Page 10: ...10 DDR2 LP Compliance Testing Methods of Implementation ...
Page 46: ...2 Preparing to Take Measurements 30 DDR2 LP Compliance Testing Methods of Implementation ...
Page 70: ...3 Measurement Clock Tests 54 DDR2 LP Compliance Testing Methods of Implementation ...
Page 224: ...14 Clock Timing CT Tests 208 DDR2 LP Compliance Testing Methods of Implementation ...
Page 270: ...15 Data Strobe Timing DST Tests 254 DDR2 LP Compliance Testing Methods of Implementation ...