Keysight Technologies D9020DDRC, Manual

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DDR2(+LP) Compliance Testing Methods of Implementation 131
Single-Ended Signals AC parameter tests for Clocks 8
V
IHCKE
Test - Input Logic High (Clock Enable) - Test Method of Implementation
The purpose of this test is to verify that the mode of histogram of the high level voltage value of the
test signal within a valid sampling window is greater than the conformance lower limits of the V
IHCKE
value specified in the JEDEC specification.
The value of V
DDCA
which directly affect the conformance lower limit is set to 1.2V for the compliance
limit set used. User may choose to use the UDL (User Defined Limit) feature in the application to
perform this test against a customize test limit set based on different values of V
DDCA
.
Signals of Interest
Mode Supported: LPDDR2 only
Signal cycle of interest: WRITE
Required Read/Write separation: NO
Signal(s) of Interest:
• Clock Enable Signal
Signals required to perform the test on the oscilloscope:
• Pin Under Test, PUT - any of the signal of interest defined above
Test Definition Notes from the Specification
Test References
See Table 75 - Single-ended AC and DC Input Levels for CKE in the JESD209-2B .
PASS Condition
The mode value for the high level voltage shall be greater than or equal to the minimum V
IHCKE
value.
Measurement Algorithm
1 Sample/acquire signal data.
2 Find all valid positive pulses. A valid positive pulse starts at V
REF
crossing at valid rising edge and
end at V
REF
crossing at the following valid falling edge (See notes on threshold).
3 Zoom in on the first valid positive pulse and perform V
TOP
measurement. Take the V
TOP
measurement results as V
IHCKE
value.
4 Continue the previous step with another 9 valid positive pulses.
5 Determine the worst result from the set of V
IHCKE
measured.
Table 79 LPDDR2 Single-ended AC and DC Input Levels for CKE
Symbol Parameter Min Max Units Notes
V
IHCKE
CKE Input High Level 0.8 * V
DDCA
Note 1 V 1