Keysight Technologies D9020DDRC, Manual

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DDR2(+LP) Compliance Testing Methods of Implementation 261
Data Timing Tests 16
tDH(base), Differential DQ and DM Input Hold Time - Test Method of Implementation
The purpose of this test is to verify that the time interval from the data or data mask (DQ/DM
rising/falling edge) hold time to the associated DQS crossing edge is within the conformance limits
as specified in the JEDEC specification.
Signals of Interest
Mode Supported: DDR2, LPDDR2
Signal cycle of interest: WRITE
Signal(s) of Interest:
• Data Signal (supported by Data Strobe Signal)
• Data Mask Signal
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQ signals from different rank of memory)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ or Data Mask Signal, DM
• Data Strobe Signal, DQS (this must use a differential DQS connection)
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Table 175 Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) & (DDR2-667 and DDR2-800)
Parameter Symbol DDR2-400 DDR2-533 Units Specific Notes
Min Max Min Max
DQ and DM input hold time (differential strobe) tDH(base) 275 x 275 x ps 6,7,8,21,28
Parameter Symbol DDR2-667 DDR2-800 Units Specific Notes
Min Max Min Max
DQ and DM input hold time tDH(base) 175 x 125 x ps 6,7,8,21,28,31
Table 176 Timing Parameters by Speed Grade (DDR2-1066)
Parameter Symbol DDR2-1066 Units Specific Notes
Min Max
DQ and DM input hold time tDH(base) 75 x ps 6,7,8,18,23,26
Table 177 Data Setup and Hold Base Values
Symbol LPDDR2 Unit Reference
1066 933 800 677 533 466
tDH(base) 80 105 140 220 300 320 ps V
IH/L(AC)
= V
REF(DC)
+/- 130mV