Keysight Technologies D9020DDRC, Manual

Page: 87 / 370

DDR2(+LP) Compliance Testing Methods of Implementation 71
Single-Ended Signals AC Input Parameters Tests 4
Test References
See Table 20 - Input AC Logic Level, in the JEDEC Standard JESD79-2E and Table 20 - Input AC
Logic Level in the JESD208 .
PASS Condition
The voltage level at tDS (DM and DQ input setup time in JEDEC specification) before DQS midpoint
for the low level voltage shall be less than or equal to the maximum V
IL(AC)
value.
Measurement Algorithm
1 Acquire and split read and write burst of the acquired signal.
2 Take the first valid WRITE burst found.
3 Find all valid falling DQ crossings that cross V
IL(AC)
in the burst.
4 For all DQ crossings found, locate all the following DQS crossings that cross Midpoint. (0V for
differential DQS and V
REF
for single ended DQS)
5 Calculate the time where the test result is taken. Calculation is expressed as
T
TESTRESULT
= T
DQS MIDPOINT
- tDS.
(tDS - DM and DQ input setup time in JEDEC specification which is due to speed grade.)
6 Take voltage level of DQ signal at T
TESTRESULT
as the test result for V
IL(AC)
.
7 Collect all V
IL(AC)
.
8 Determine the worst result from the set of V
IL(AC)
measured.