Keysight Technologies D9020DDRC, Manual

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DDR2(+LP) Compliance Testing Methods of Implementation 271
Data Timing Tests 16
See Table 41 - Timing Parameters by Speed Grade (DDR2- 1066) and Table 42 - DDR2- 1066
tDS/tDH Derating with Differential Data Strobe in the
JESD208 .
Also see Table 108 - Data Setup and Hold Base-Values, Table 109 - Derating Values LPDDR2
tDS/tDH - AC/DC Based AC220 and Table 110 - Derating Values LPDDR2 tDS/tDH - AC/DC Based
AC300 in the
JESD209-2B .
PASS Condition
The worst measured tDS shall be within the specification limit.
Measurement Algorithm
1 Acquire and split read and write burst of the acquired signal.
2 Take the first valid WRITE burst found.
3 Find all valid rising DQ crossings that cross V
IH(AC)
in the burst.
4 Find all valid falling DQ crossings that cross V
IL(DC)
in the same burst.
5 For all DQ crossings found, locate all next DQS crossings that cross 0V.
6 tDS is defined as the time between the DQ crossing and the DQS crossing.
7 Collect all tDS.
8 Find the worst tDS among the measured values and report the value as the test result.
9 Measure the mean slew rate for all the DQ and DQS edges.
10 Use the mean slew rate for DQ and DQS to determine the ∆tDS derating value based on the
derating tables.
11 The test limit for tDS test = tDS(base) + ∆tDS.