Keysight Technologies D9020DDRC, Manual

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15 Data Strobe Timing (DST) Tests
216 DDR2(+LP) Compliance Testing Methods of Implementation
tLZ(DQ), DQ Low-Impedance Time from CK/CK# - Test Method of Implementation
The purpose of this test is to verify that the time when the DQ starts driving (from high impedance
state to HIGH/LOW state), to the clock signal crossing, is within the conformance limit as specified in
the JEDEC specification.
Signals of Interest
Mode Supported: DDR2, for LPDDR2 refer to tLZ(DQS) Test (Low Power)
Signal cycle of interest: READ
Signal(s) of Interest:
• Data Signal (supported by Data Strobe Signal)
• Clock Signal (CK as Reference Signal)
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQ signals from different rank of memory)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ
• Data Strobe Signal, DQS
• Clock Signal, CK
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Test References
See Table 41 - Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) and Table 42 -
Timing Parameters by Speed Grade (DDR2-667 and DDR2-800), in the
JEDEC Standard JESD79-2E .
Also see Table 41 - Timing Parameters by Speed Grade (DDR2-1066) in the JESD208 .
Table 130 Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) & (DDR2-667 and DDR2-800)
Parameter Symbol DDR2-400 DDR2-533 Units Specific
Notes
Min Max Min Max
DQ LOW impedance time from CK/CK tLZ(DQ) 2 x tAC min tAC max 2 x tAC min tAC max ps 18
Parameter Symbol DDR2-667 DDR2-800 Units Specific
Notes
Min Max Min Max
DQ LOW impedance time from CK/CK tLZ(DQ) 2 x tAC min tAC max 2 x tAC min tAC max ps 18, 40
Table 131 Timing Parameters by Speed Grade (DDR2-1066)
Parameter Symbol DDR2-1066 Units Specific
Notes
Min Max
DQ LOW impedance time from CK/CK tLZ(DQ) 2 x tAC min tAC max ps 15,35