Keysight Technologies D9020DDRC, Manual

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17 Command and Address Timing (CAT) Tests
322 DDR2(+LP) Compliance Testing Methods of Implementation
tISCKE, CKE Input Setup Time - Test Method of Implementation
The purpose of this test is to verify that the time interval from Clock Enable signal (CKE rising/falling
edge) setup time to the associated clock crossing edge must be within the conformance limit as
specified in the JEDEC specification.
Signals of Interest
Mode Supported: LPDDR2 only
Signal cycle of interest: WRITE
Require Read/Write Separation: No
Signal(s) of Interest:
• Clock Enable Signal
Signals required to perform the test on the oscilloscope:
• Clock Enable Signal
• Clock Signal
Test Definition Notes from the Specification
Test References
See Table 103 - LPDDR2 AC Timing Table in the JEDEC Standard JESD209-2B .
PASS Condition
The measured time interval between Clock Enable (CKE) setup time to respective clock crossing
point shall be within the specification limit.
Measurement Algorithm
1 Pre-condition the oscilloscope.
2 Triggered on either rising or falling edge of the Clock Enable signal under test.
3 Find all crossings on rising edge of the signal under test that cross V
IH(AC)
.
4 Find all crossings on falling edge of the signal under test that cross V
IL(AC)
.
5 For all the crossings found, locate the nearest rising Clock crossings on the right that cross 0V.
6 Take the time difference of the signal under test's crossings to the corresponding clock crossing
as tISCKE.
7 Collect all measured tISCKE.
8 Report the worst tISCKE measured as test result.
9 Compare the test result to the compliance test limit.
Table 231 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
CKE Input Parameters*
14
CKE input
setup time
tISCKE Min
0.25 t
CK(avg)