Keysight Technologies D9020DDRC, Manual

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14 Clock Timing (CT) Tests
196 DDR2(+LP) Compliance Testing Methods of Implementation
tDQSCK, DQS Output Access Time from CK/CK #- Test Method of Implementation
The purpose of this test is to verify that the time interval from the data strobe output (DQS rising and
falling edge) access time to the nearest rising or falling edge of the clock is within the conformance
limit as specified in the JEDEC specification.
Signals of Interest
Signal cycle of interest: READ
Mode Supported: DDR2, for LPDDR2 refer to tDQSCK Test (Low Power)
Signal(s) of Interest:
• Data Strobe Signal (supported by Data Signal)
• Clock Signal (CK as Reference Signal)
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQ signals from different rank of memory.)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ
• Data Strobe Signal, DQS
• Clock Signal, CK
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Test References
See Table 41 - Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) and Table 42 -
Timing Parameters by Speed Grade (DDR2-667 and DDR2-800) in the
JEDEC Standard JESD79-2E .
Also see Table 41 - Timing Parameters by Speed Grade (DDR2-1066) in the JESD208 .
Table 119 Timing Parameters by Speed Grade (DDR2-400 and DDR2-533) & (DDR2-667 and DDR2-800)
Parameter Symbol DDR2-400 DDR2-533 Units Specific Notes
Min Max Min Max
DQS output access time from CK/CK tDQSCK -500 +500 -450 +450 ps
Parameter Symbol DDR2-667 DDR2-800 Units Specific Notes
Min Max Min Max
DQS output access time from CK/CK tDQSCK -400 400 -350 350 ps 40
Table 120 Timing Parameters by Speed Grade (DDR2-1066)
Parameter Symbol DDR2-1066 Units Specific Notes
Min Max
DQS output access time from CK/CK tDQSCK -325 325 ps 35