Keysight Technologies D9020DDRC, Manual

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15 Data Strobe Timing (DST) Tests
240 DDR2(+LP) Compliance Testing Methods of Implementation
tHZ(DQ) Test (Low Power), DQ Out HIGH Impedance Time From Clock - Test Method of Imple -
mentation
The purpose of this test is to verify that the time when the DQ is no longer driving (from HIGH state
OR LOW state to the high impedance stage), to the reference clock signal crossing, is within the
conformance limits as specified in the JEDEC specification.
Signals of Interest
Mode Supported: LPDDR2, for DDR2 refer to the tHZ(DQ) Test
Signal cycle of interest: READ
Signal(s) of Interest:
• Data Signal (supported by Data Strobe Signal)
• Clock Signal
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQ signals from different rank of memory)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ
• Data Strobe Signal, DQS
• Clock Signal, CK
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Test References
See Table 103 - LPDDR2 AC Timing Table in the JESD209-2B .
PASS Condition
The measured tHZ(DQ) shall be within the specification limit.
Table 164 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Read Parameters*
14
DQ high-Z from
clock
*15
tHZ(DQ) Max
t
DQSCK
(max) + {1.4 * t
DQSQ
(max)} ps