Keysight Technologies D9020DDRC, Manual

Page: 309 / 370

DDR2(+LP) Compliance Testing Methods of Implementation 293
Data Timing Tests 16
tDS, DQ and DM Input Setup Time (Differential - V
REF
based) - Test Method of Implementation
The purpose of this test is to verify that the time interval from data or data mask (DQ/DM
rising/falling edge) setup time to the associated DQS crossing edge must be within the conformance
limit as specified in the JEDEC specification.
Signals of Interest
Mode Supported: LPDDR2 only
Signal cycle of interest: Write
Require Read/Write separation: Yes
Signal(s) of Interest:
• Data Signal (supported by Data Strobe Signal) OR
• Data Mask Signal (supported by Data Strobe Signal)
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQ signals from different rank of memory)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ or Data Mask Signal, DM
• Data Strobe Signal, DQS (This must use a differential DQS connection)
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Test References
See Table 103 - LPDDR2 AC Timing Table in the JEDEC Standard JESD209-2B .
PASS Condition
The worst measured tDS should be within the specification limit.
Table 203 LPDDR2 AC Timing Table
Parameter Symbol Min
Max Min
t
CK
LPDDR2 Unit
1066 933 800 677 533 466*
5
400 333 266*
5
200*
5
Write Parameters*
14
DQ and DM input
setup time (Vref
based)
tDS Min
210 235 270 350 430 450 480 600 750 1000 ps