Keysight Technologies D9020DDRC, Manual

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DDR2(+LP) Compliance Testing Methods of Implementation 283
Data Timing Tests 16
tDS1(derate), Single-Ended DQ and DM Input Setup Time with Derating Support - Test Meth -
od of Implementation
The purpose of this test is to verify that the time interval from the data or data mask (DQ/DM
rising/falling edge) setup time to the associated DQS edge is within the conformance limits as
specified in the JEDEC specification.
Signals of Interest
Mode Supported: DDR2 only
Signal cycle of interest: WRITE
Signal(s) of Interest:
• Data Signal (supported by Data Strobe Signal)
• Data Mask Signal
Optional signal(s):
• Chip Select Signal (this signal is used to separate DQ signals from different rank of memory)
Signals required to perform the test on the oscilloscope:
• Data Signal, DQ or Data Mask Signal, DM
• Data Strobe Signal, DQS (this must use a differential DQS connection)
• Chip Select Signal, CS (optional)
Test Definition Notes from the Specification
Table 196 Timing Parameters by Speed Grade (DDR2-400 and DDR2-533)
Parameter Symbol DDR2-400 DDR2-533 Units Specific Notes
Min Max Min Max
DQ and DM input setup time (single-ended strobe) tDS1(base) 25 x -25 x ps 6,7,8,25
Table 197 DDR2-400/533 tDS1/tDH1 derating with single-ended data strobe
∆
tDS1,
∆
tDH1 derating values for DDR2-400, DDR2-533 (All units in ‘ps’; the note applies to the entire table.)
DQS, Single-Ended Slew Rate
2.0 V/ns 1.5 V/ns 1.0 V/ns 0.9 V/ns
∆
tDS
∆
tDH
∆
tDS
∆
tDH
∆
tDS
∆
tDH
∆
tDS
∆
tDH
DQ Slew Rate V/ns 2.0 188 188 167 146 125 63 - -
1.5 146 167 125 125 83 42 81 43
1.0 63 125 42 83 0 0 -2 1
0.9 - - 31 69 -11 -14 -13 -13
0.8 - - - - -25 -31 -27 -30
0.7 - - - - - - -45 -53
0.6 - - - - - - - -
0.5 - - - - - - - -
0.4 - - - - - - - -