Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 381
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Integer Load and Store Instructions
R
Load Instructions
Integer-load instructions read an operand from memory and store it in a GPR destination
register,
r D. Each type of load is characterized by what they do with unused high-order
bits in r D when the operand size is less than a word (32 bits). Load-and-zero instructions
clear the unused high-order bits in r D to zero. Load-algebraic instructions fill the unused
high-order bits in r D with a copy of the most-significant bit in the operand.
Load-with-update instructions are provided, but the following two rules apply:
• r A must not be equal to 0. If r A
=
0, the instruction form is invalid.
• r A must not be equal to r D. If r A
=
r D, the instruction form is invalid.
In the PPC405, the above invalid instruction forms produce a boundedly-undefined result.
In other PowerPC implementations, those forms can cause a program exception.
Load Byte and Zero
Table 3-14 lists the PowerPC load byte and zero instructions. These instructions load a byte
from memory into the lower-eight bits of r D and clear the upper-24 bits of r D to 0.
Load Halfword and Zero
Table 3-15 lists the PowerPC load halfword and zero instructions. These instructions load a
halfword from memory into the lower-16 bits of r D and clear the upper-16 bits of r D to 0.
Table 3-14: Load Byte and Zero Instructions
Mnemonic Name Addressing Mode
Operand
Syntax
lbz Load Byte and Zero Register-indirect with immediate index
EA
=
(
r
A|0)
+
d
r D,d( r A)
lbzu
Load Byte and Zero with Update Register-indirect with immediate index
EA
=
( r A)
+
d
r A
←
EA
r
A
≠
0,
r
A
≠
r
D
lbzx
Load Byte and Zero Indexed Register-indirect with index
EA
=
(
r
A|0)
+
(
r
B)
r
D,
r
A,
r
B
lbzux
Load Byte and Zero with Update
Indexed Register-indirect with index
EA
=
( r A)
+
( r B)
r
A
←
EA
r
A
≠
0,
r
A
≠
r
D