484
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 6:
Virtual-Memory Management
R
These instructions are not address-specific and can affect multiple pages with
different access protections. Because they are privileged instructions, access cannot be
denied by zone protection.
-
dccci
—Affected by TLBLO[WR] only. This instruction can cause data loss by
invalidating modified data in the cache-congruence class.
-
iccci
—Not affected by TLBLO[WR]. The instruction cache cannot hold modified
data.
Both
dccci
and
iccci
can cause TLB-miss interrupts. Because these instructions are not
address-specific, it is recommended that software does not execute them when data-
relocation is enabled (MSR[DR]=1).
•
Some cache-control instructions update system memory with data already present in
the cache. These instructions are treated as loads (reads) by the access-protection
mechanism rather than as stores. The reason is that stores were already used to place
the modified data into the cache and passed the access-protection check. Therefore,
these instructions are not affected by TLBLO[WR].
-
dcbf
—Affected by ZPR[Z
n
]=00 in user mode only.
-
dcbst
—Affected by ZPR[Z
n
]=00 in user mode only.
•
Speculative cache-control instructions are restricted by TLB write-protection access
control and by zone protection. However, if these instructions fail access protection
checks they do not cause an exception and are instead treated as a “no operation”.
-
dcba
—Affected by TLBLO[WR] and (in user mode only) ZPR[Z
n
]=00.
-
dcbt
—Affected by ZPR[Z
n
]=00 in user mode only. This instruction is treated as a
load and is therefore not affected by TLBLO[WR].
-
dcbtst
—Affected by ZPR[Z
n
]=00 in user mode only. This instruction is treated as
a load and is therefore not affected by TLBLO[WR].
-
icbt
—Affected by ZPR[Z
n
]=00 in user mode only. This instruction is treated as a
load and is therefore not affected by TLBLO[WR].
•
Certain privileged cache-control instructions are treated as loads and are therefore
unaffected by TLBLO[WR]. Because they are privileged instructions, access cannot be
denied when ZPR[Z
n
]=00. These instructions are:
-
dcread
.
-
icbi
.
-
icread
.
summarizes the effect of access violations that occur when a cache-control
instruction is executed. In this table, the “Read-Only Page” column applies to the
execution of an instruction in privileged mode and (for the non-privileged instructions)
user mode. The “No-Access Allowed Page” column applies to the execution of instructions
only in user mode (no-access allowed protection is not available in supervisor mode).
Table 6-4:
Effect of Cache-Control Instruction Access Violations
Instruction
Read-Only Page
(TLBLO[WR]=0)
No-Access Allowed Page
(ZPR[Z
n
]=00)
dcba
No operation.
No operation.
dcbf
No violation—treated as load.
Data-storage interrupt.
dcbi
Data-storage interrupt.
No violation—privileged instruction.
dcbst
No violation—treated as load.
Data-storage interrupt.
dcbt
No violation—treated as load.
No operation.
dcbtst
No violation—treated as load.
No operation.
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