324
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 1:
Introduction to the PPC405
R
Exception Model
The
exception model
defines the set of exceptions and the conditions that can cause those
exceptions. The model specifies exception characteristics, such as whether they are precise
or imprecise, synchronous or asynchronous, and maskable or non-maskable. The model
defines the exception vectors and a set of registers used when interrupts occur as a result of
an exception. The model also provides memory space for implementation-specific
exceptions.
Memory-Management Model
The
memory-management model
defines how memory is partitioned, configured, and
protected. The model also specifies how memory translation is performed, defines special
memory-control instructions, and specifies other memory-management characteristics.
Time-Keeping Model
The
time-keeping model
defines resources that permit the time of day to be determined and
the resources and mechanisms required for supporting timer-related exceptions.
PowerPC Architecture Levels
These above
aspects of the PowerPC architecture are defined at three levels . This layering
provides flexibility by allowing degrees of software compatibility across a wide range of
implementations. For example, an implementation such as an embedded controller can
support the user instruction set, but not the memory management, exception, and cache
models where it might be impractical to do so.
The three levels of the PowerPC architecture are defined in
The PowerPC architecture requires that all PowerPC implementations adhere to the UISA,
offering compatibility among all PowerPC application programs. However, different
versions of the VEA and OEA are permitted.
Embedded applications written for the PPC405 are compatible with other PowerPC
implementations. Privileged software generally is not compatible. The migration of
Table 1-1:
Three Levels of PowerPC Architecture
User Instruction-Set Architecture
(UISA)
Virtual Environment Architecture
(VEA)
Operating Environment
Architecture (OEA)
•
Defines the architecture level to
which user-level (sometimes
referred to as problem state)
software should conform
•
Defines the base user-level
instruction set, user-level
registers, data types, floating-
point memory conventions,
exception model as seen by user
programs, memory model, and
the programming model
•
Defines additional user-level
functionality that falls outside
typical user-level software
requirements
•
Describes the memory model for
an environment in which
multiple devices can access
memory
•
Defines aspects of the cache
model and cache-control
instructions
•
Defines the time-base resources
from a user-level perspective
•
Defines supervisor-level
resources typically required by
an operating system
•
Defines the memory-
management model, supervisor-
level registers, synchronization
requirements, and the exception
model
•
Defines the time-base resources
from a supervisor-level
perspective
Note:
All PowerPC implementations
adhere to the UISA.
Note:
Implementations that conform
to the VEA level are guaranteed to
conform to the UISA level.
Note:
Implementations that conform
to the OEA level are guaranteed to
conform to the UISA and VEA levels.
Содержание Virtex-II Pro PPC405
Страница 1: ...R Volume 2 a PPC405 User Manual Virtex II Pro Platform FPGA Developer s Kit March 2002 Release...
Страница 14: ...322 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation Preface R...
Страница 252: ...560 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation R...
Страница 260: ...568 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation R...
Страница 562: ...870 www xilinx com March 2002 Release 1 800 255 7778 Virtex II Pro Platform FPGA Documentation R...
