Xilinx Virtex-II Pro PPC405, Руководство пользователя

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456 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 5: Memory-System Management
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When a bit in the SLER is cleared to 0, the specified memory region is accessed using big-
endian ordering. When the bit is set to 1, the specified memory region is accessed using
little-endian ordering.
After a processor reset, all bits in the SLER are cleared to 0. This specifies big-ending
accesses for all real-mode memory.
The SLER is a privileged SPR with an address of 955 (0x3BB) and can be read and written
using the
mfspr and mtspr instructions.
Cache Control
Cache Instructions
The following sections describe the user and privileged instructions used in cache
management. Within the instruction name, the term
cache block often appears. A cache
block is synonymous with a cacheline.
Table 5-3 summarizes which cache-control instructions are privileged and which
instructions can be executed in user mode.
Instruction-Cache Control Instructions
Table 5-4 shows the instruction-cache control instructions supported by the PPC405. These
instructions provide the ability to invalidate the entire cache array or a single cacheline,
prefetch instructions into the cache, and debug the cache.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 5-12: Storage Little-Endian Register (SLER)
Table 5-3: Privileged and User Cache-Control Instructions
Instruction Cache Data Cache
Mnemonic Privilege Level Mnemonic Privilege Level
icbi User dcba User
icbt User dcbf User
iccci Privileged dcbi Privileged
icread Privileged dcbst User
dcbt User
dcbtst User
dcbz User
dccci Privileged
dcread Privileged