Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 457
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Cache Control
R
Data-Cache Control Instructions
Table 5-5 shows the data-cache control instructions supported by the PPC405. These
instructions provide the ability to invalidate the entire cache array or a single cacheline,
prefetch data into the cache, and debug the cache.
Table 5-4: Instruction-Cache Control Instructions
Mnemonic Name Operation
Operand
Syntax
icbi Instruction Cache Block Invalidate If the instruction specified by the effective address
(EA) is cached by the instruction cache, the
cacheline containing that instruction is invalidated.
EA is calculated using register-indirect with index
addressing:
EA
=
( r A|0)
+
( r B)
r A, r B
icbt Instruction Cache Block Touch If the instruction specified by the effective address
(EA) is cacheable and is not currently cached by the
instruction cache, the cacheline containing that
instruction is loaded into the instruction cache
from system memory.
EA is calculated using register-indirect with index
addressing:
EA
=
( r A|0)
+
( r B)
r A, r B
iccci Instruction Cache Congruence Class
Invalidate Invalidates the entire instruction cache. —
icread Instruction Cache Read If the instruction specified by the effective address
(EA) is cached by the instruction cache, the
ICDBDR register is loaded with information from
one of the two ways indexed by the EA. CCR0
fields specify the cache way, and whether the
instruction tag or instruction word is loaded into
the ICDBDR. See
icread Instruction , page 468 for
more information.
EA is calculated using register-indirect with index
addressing:
EA
=
( r A|0)
+
( r B)
r A, r B