Xilinx Virtex-II Pro PPC405, Руководство пользователя

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468 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 5: Memory-System Management
R
! r N contains a modified instruction.
stw r N, addr1 ! Store the modified instruction.
dcbst
addr1 ! Force instruction to be written to system memory.
sync ! Wait for the system-memory update.
icbi addr1 ! Invalidate unmodified instruction-cache entry.
isync ! The unmodified instruction might be in the
! prefetch buffers. isync invalidates the prefetch
! buffers.
Cache Debugging
The PPC405 provides two instructions that can read cache-tag and cache-data information
for a specific cache congruence class.
icread performs this function for the instruction
cache and dcread performs this function for the data cache. These instructions operate
under the control of certain bit fields in the CCR0 register (see Core-Configuration
Register , page 459 ). The operation of each instruction is described in the following
sections.
icread Instruction
The icread instruction reads instruction cacheline information for a specific effective
address. A congruence class is selected from the instruction cache using the effective-
address bits EA
22:26
. A way is selected from the congruence class using the cache-way select
field (CWS) in the CCR0 register. CCR0[CWS]
=
0 selects way A and CCR0[CWS]
=
1 selects
way B. The cacheline information in the selected congruence-class and way is loaded into
the 32-bit instruction-cache debug-data register (ICDBDR).
Figure 5-15 shows the format
of the ICDBDR. The fields in the ICDBDR are defined as shown in Table 5-8 .
The ICDBDR is a privileged, read-only SPR with an address of 979 (0x3D3). It can be read
using the
mfspr instruction.
0 22 27 28 31
INFO V LRU
Figure 5-15: Instruction-Cache Debug-Data Register (ICDBDR)
Table 5-8: Instruction-Cache Debug-Data Register (ICDBDR) Field Definitions
Bit Name Function Description
0:21 INFO Instruction-Cache Information
CCR0[CIS]
=
0—Instruction
word.
CCR0[CIS]
=
1—Instruction tag.
Contains either the cacheline tag or a single instruction word from
the cacheline. If an instruction word is loaded, it is specified using
effective-address bits EA
27:29
. CCR0[CIS] controls the type of
information loaded into this field.
22:26 Reserved
27 V Valid
0—Cacheline is not valid.
1—Cacheline is valid.
Contains a copy of the cacheline valid bit.
28:30 Reserved
31 LRU Least-Recently Used
0—Way A is least-recently
used.
1—Way B is least-recently
used.
Contains the LRU bit for the congruence class associated with the
cacheline.