632
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 11:
Instruction Set
R
icbt
Instruction Cache Block Touch
Description
An effective address (EA) is calculated by adding an index to a base address, which are
formed as follows:
•
The contents of register
r
B are used as the index.
•
If the
r
A field is 0, the base address is 0.
•
If the
r
A field is not 0, the contents of register
r
A are used as the base address.
If EA is cachable but not in the instruction cache, the corresponding cacheline is loaded
into the instruction cache from main memory. If EA is already cached, or if the storage
attributes indicate the EA is not cachable, no operation is performed.
This instruction is a hint to the processor that the program will likely execute the
instruction referenced by the EA in the near future. The processor can potentially improve
performance by loading the cacheline into the instruction cache.
Pseudocode
EA
←
(
r
A|0) + (
r
B)
Prefetch instruction-cacheline corresponding to EA
Registers Altered
•
None.
Exceptions
This instruction is considered a “load” with respect to data-storage exceptions. However,
this instruction does not cause data storage exceptions or data TLB-miss exceptions. If
conditions occur that would cause these exceptions,
icbt
is treated as a no-op. This
instruction is also considered a “load” with respect to data address-compare (DAC) debug
exceptions. Debug exceptions can occur as a result of executing this instruction.
Instruction-storage exceptions and instruction TLB-miss exceptions are associated with
instruction
fetching
, not with instruction
execution
. Exceptions that occur during the
execution of instruction-cache operations cause data-storage exceptions and data TLB-
miss exceptions.
Execution of any of the following invalid-instruction forms results in a boundedly-
undefined result rather than a program exception:
•
Reserved bits containing a non-zero value.
icbt
r
A,
r
B
X Instruction Form
31
0
0
0
0
0
r
A
r
B
262
0
0
6
1
1
1
6
2
1
3
1
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