Xilinx Virtex-II Pro PPC405, Руководство пользователя

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352 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 2: Operational Concepts
R
instruction memory changes, the ICU must be made coherent with the updates. This is
accomplished by invalidating the ICU and updating the instruction memory with
instructions using the new endian ordering. Subsequent fetches from the updated memory
region are interpreted correctly before they are cached and decoded. See
Instruction-
Cache Control Instructions , page 456 for information on instruction-cache invalidation.
Little-Endian Data Accesses
Unlike instruction fetches, data accesses from little-endian memory regions are not byte-
reversed between memory and the data-cache unit (DCU). The data-byte ordering stored
in memory depends on the data size (byte, halfword, or word). The data size is not known
until the data item is moved between memory and a general-purpose register. In the
PPC405, byte reversal of load and store accesses is performed between the DCU and the
GPRs.
When accessing data in a little-endian memory region, the processor automatically does
the following regardless of data alignment:
• For byte loads/stores, no reordering occurs
• For halfword loads/stores, bytes are reversed within the halfword
• For word loads/stores, bytes are reversed within the word
The big-endian and little-endian mappings of the structure s , shown in Structure-
Mapping Examples , page 349 , demonstrate how the size of a data item determines its byte
ordering. For example:
• The word a has its four bytes reversed within the word spanning addresses 0x00–0x03
• The halfword e has its two bytes reversed within the halfword spanning addresses
0x1C–0x1D
• The array of bytes d (where each data item is a byte) is not reversed when the big-
endian and little-endian mappings are compared (For example, the character 'A' is
located at address 14 in both the big-endian and little-endian mappings)
In little-endian memory regions, data alignment is treated as it is in big-endian memory
regions. Unlike little-endian mode in the PowerPC architecture, no special alignment
exceptions occur when accessing data in little-endian memory regions versus big-endian
regions.
Load and Store Byte-Reverse Instructions
When accessing big-endian memory regions, load/store instructions move the more-
significant register bytes to and from the lower-numbered memory addresses and the less-
significant register bytes are moved to and from the higher-numbered memory addresses.
The
load/store with byte-reverse instructions, as described in Load and Store with Byte-
Reverse Instructions , page 385 , do the opposite. The more-significant register bytes are
moved to and from the higher-numbered memory addresses, and the less-significant
register bytes are moved to and from the lower-numbered memory addresses.
Even though the load/store with byte-reverse instructions can be used to access little-
endian memory, the E storage attribute provides two advantages over using those
instructions:
• The load/store with byte-reverse instructions do not solve the problem of fetching
instructions from a little-endian memory region. Only the E storage attribute
mechanism supports little-endian instruction fetching.
• Typical compilers cannot make general use of the load/store with byte-reverse
instructions, so these instructions are normally used only in device drivers written in
hand-coded assembler. However, compilers can take full advantage of the E storage-
attribute mechanism, allowing application programmers working in a high-level
language, such as C, to compile programs and data structures using little-endian
ordering.