530
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 8:
Timer Resources
R
The following sections describe the use of the timer-event registers in managing the
interrupts.
Watchdog-Timer Events
The watchdog timer can aid in recovery from software or hardware failure. It can be
programmed to cause a watchdog time-out (also called the watchdog event) after a fixed
time-period elapses. Watchdog time-outs can be further programmed to cause a critical
interrupt called the watchdog interrupt. Normally, the watchdog-interrupt handler clears
the watchdog event before returning. However, if a software or hardware failure prevents
the interrupt handler from clearing the event, a subsequent watchdog time-out can be
programmed to force a reset.
Watchdog interrupts are enabled when
both
of the following bits are set to 1:
•
The watchdog-interrupt enable bit in the timer-control register, TCR[WIE]
.
•
The critical-interrupt enable bit in the machine-state register, MSR[CE]
.
If either TCR[WIE]
=
0 or MSR[CE]
=
0, watchdog-timer interrupts are disabled. However,
watchdog time-outs can be programmed to force a reset whether or not the watchdog
interrupt is enabled.
A watchdog time-out occurs when a selected bit in the time-base lower register (TBL)
changes from 0 to 1. The watchdog-period bit in the timer-control register (TCR[WP]) is
used to select the TBL bit that controls the time-out, as shown in
Software cannot disable watchdog time-outs. This is because the time-base register is
always incrementing and a valid watchdog interval is always specified by TCR[WP].
Instead of preventing watchdog time-outs, software controls the action taken by the
processor when a time-out occurs by managing the watchdog-event state machine. A
timer-control register field and two timer-status register bits are used to control the state
machine:
•
Watchdog-reset control
, TCR[WRC]—This field specifies the type of reset to be
performed when the state machine enters the reset state:
-
00—No reset. The processor ignores the watchdog time-out.
-
01—A processor-only reset occurs. No external devices are reset.
-
10—A chip reset occurs. The processor and all external devices on the same chip
are reset. No other system components are reset.
-
11—The entire system, including the processor and chip, are reset.
Each bit in TCR[WRC] is sticky. Software can set these bits but cannot clear them. After
a bit is set only a reset can clear it.
•
Enable next watchdog
, TSR[ENW]—This bit performs the following functions:
-
When cleared to 0, the TSR[WIS] bit is not updated or used by the processor.
Watchdog time-outs cannot cause an interrupt or reset. The next watchdog time-
out sets this bit to 1.
Table 8-5:
Watchdog Time-Out Periods
TCR[WP]
Selected TBL Bit
Time-Base
Clock Period
Watchdog Period
(300 MHz Clock)
00
15
2
17
0.437 msec
01
11
2
21
6.99 msec
10
7
2
25
0.112 sec
11
3
2
29
1.79 sec
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