Xilinx Virtex-II Pro PPC405, Руководство пользователя

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Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
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Appendix B
Instruction Summary
This appendix lists the PPC405 instruction set sorted by mnemonic, opcode, function, and
form. A reference table containing general instruction information such as the architecture
level, privilege level, and compatibility is also provided.
In the following tables, reserved fields are shaded gray and contain a value of zero.
Instructions Sorted by Mnemonic
Table B-1 lists the PPC405 instruction set in alphabetical order by mnemonic.
Table B-1: Instructions Sorted by Mnemonic
0 6 9 11 12 14 16 17 20 21 22 26 30 31
add 31 r D r A r B OE 266 Rc
addc 31 r D r A r B OE 10 Rc
adde 31 r D r A r B OE 138 Rc
addi 14 r D r A SIMM
addic 12 r D r A SIMM
addic. 13 r D r A SIMM
addis 15 r D r A SIMM
addme 31 r D r A 00000 OE 234 Rc
addze 31 r D r A 00000 OE 202 Rc
and 31 r S r A r B 28 Rc
andc 31 r S r A r B 60 Rc
andi. 28 r S r A UIMM
andis. 29 r S r A UIMM
b 18 LI AA LK
bc 16 BO BI BD AA LK
bcctr 19 BO BI 00000 528 LK
bclr 19 BO BI 00000 16 LK
cmp 31 crf D 00 r A r B 0 0
cmpi 11 crf D 00 r A SIMM
cmpl 31 crf D 00 r A r B 32 0
cmpli 10 crf D 00 r A SIMM