488
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 6:
Virtual-Memory Management
R
TLB entries are normally modified by interrupt handlers. The shadow TLB is
automatically invalidated when an interrupt occurs. The interrupt also disables address
translation, placing the processor in real mode. The MMU does not access the UTLB or
update the shadow TLBs when address translation is disabled. If the interrupt handler
updates the UTLB and returns from the interrupt handler (using
rfi
) without enabling
virtual mode, no additional context synchronization is required.
However, if virtual mode is enabled by the interrupt handler and the UTLB is updated,
those updates are not synchronized with the shadow TLBs until an
rfi
is executed to exit
the handler. If UTLB updates must be reflected in the shadow TLB while the interrupt
handler is executing,
isync
must be executed after updating the UTLB.
As a general rule, software manipulation of UTLB entries should always be followed by a
context-synchronizing operation, typically an
isync
instruction.
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