Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 839
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Synchronization Examples
R
loop: lwarx r 5,0, r 3 #load and reserve
cmpwi r 5, 0 #compare with 0
bne
$+12 #branch if not equal to 0
stwcx. r 4,0, r 3 #try to store non-zero
bne- loop #loop if reservation lost
Compare and Swap
The compare and swap primitive atomically compares a value in a first register with a
memory word. If they are equal, it stores a value from a second register into the memory
word. If they are unequal, it moves the word from memory into the first register and
updates CR0[EQ] to reflect the comparison result. This example assumes that the address
of the memory word is in
r
3, the compare value is contained in
r
4, the new data is stored
from
r
5, and the old data is loaded into
r
6.
loop: lwarx r 6,0, r 3 #load and reserve
cmpw r 4, r 6 #compare load value with first register
bne- exit #skip if not equal
stwcx. r
5,0,
r
3 #store second register if still reserved
bne- loop #loop if reservation lost
exit: mr r 4, r 6 #move load value into first register
The following applies to the above example:
• The semantics are based on the IBM System/370™ compare and swap instruction. Some
architectures define this primitive differently.
• A compare and swap instruction is useful on machines that lack the synchronization
capability provided by the lwarx and stwcx. instructions. Although such an
instruction is atomic, it checks only whether the current value matches the old value.
An error can occur if the value is changed and restored before being tested.
• In some applications, the second bne
−
instruction and/or the mr instruction can be
omitted. The second bne- is used only to indicate that the original values in r 4 and r 6
were not equal by exiting the primitive with CR0[EQ]
=
0. If this indication is not
required by the application, the second bne- can be omitted. The mr is used only
when the application requires that the memory word be loaded into the compare
register (rather than into a third register) if the compared values are not equal. The
resulting compare and swap primitive does not obey the IBM System/370 semantics
if either or both of these instructions are omitted.
Lock Acquisition and Release
This example provides a locking algorithm that demonstrates the use of an atomic
read/modify/write synchronization operation. The argument of the lock and unlock
procedures is the address of a shared memory location (stored in
r 3). This argument points
to a lock that controls access to some shared resource, such as a data structure. The lock is
open when its value is zero and it is locked when its value is one. Before accessing the
shared resource, the processor sets the lock by having the lock procedure call test_and_set
(the procedure executes the code sequence in
Test and Set , page 838 ). This atomically
updates the old value of the lock with the new value (1) contained in r 4. The old value is
returned in r 5 (not shown in the following example). CR0[EQ] is updated by test_and_set
to indicate whether the value returned in r 5 is zero. The lock procedure repeats the
test_and_set procedure until it successfully changes the lock value from zero to one.
The processor does not access the shared resource until it sets the lock. After the bne
instruction checks for the successful test and set operation, the processor executes the isync
instruction. This synchronizes program context. The sync instruction could be used but
performance would be degraded because the sync instruction waits for all outstanding
memory accesses to complete with respect to other processors. This is not required by the
procedure.