Xilinx Virtex-II Pro PPC405, Руководство пользователя

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476 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 6: Virtual-Memory Management
R
• Data Shadow TLB —The DTLB contains eight data page-translation entries and is fully
associative. The page-translation entries stored in the DTLB represent the eight most-
frequently accessed data-page translations from the UTLB. The DTLB is used to
minimize contention between data translation and UTLB-update operations. The
initialization and management of the DTLB is controlled completely by hardware and
is transparent to software.
Figure 6-5 shows the address translation flow through the three TLBs.
Although software is not responsible for managing the shadow TLBs, software must make
sure the shadow TLBs are invalidated when the UTLB is updated. See
Maintaining
Shadow-TLB Consistency , page 487 , for more information.
TLB Entries
Figure 6-6 shows the format of a TLB entry. Each TLB entry is 68 bits and is composed of
two portions: TLBHI (also referred to as the tag entry ), and TLBLO (also referred to as the
data entry ). The fields within a TLB entry are categorized as follows:
• Virtual-page identification —These fields identify the page-translation entry. They are
compared with the virtual-page number during the translation process.
• Physical-page identification —These fields identify the translated page in physical
memory.
• Access control —These fields specify the type of access allowed in the page and are
used to protect pages from improper accesses.
Figure 6-5: ITLB/DTLB/UTLB Address Translation Flow
Generate I-side
Effective Address
Extract Real
Address from ITLB
Continue I-cache
Access
Perform ITLB
Look-up
Disabled Translation
(MSR[IR]=0)
Translation Enabled
(MSR[IR]=1)
I-Side TLB Miss
or
D-Side TLB Miss
No Translation
Translation Enabled
(MSR[DR]=1)
Translation Disabled
(MSR[DR]=0)
No Translation
Generate D-side
Effective Address
Perform DTLB
Look-up
ITLB Miss ITLB Hit
Perform UTLB
Look-up
DTLB Miss DTLB Hit
Extract Real
Address from UTLB
Access
Continue I-cache
or D-cache
UTLB Miss UTLB Hit
Extract Real
Address from DTLB
Route Address
to ITLB
Route Address
to DTLB
Exception
UG011_40a_021502