March 2002 Release
445
Virtex-II Pro™ Platform FPGA Documentation
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Memory-System Organization
R
or when explicitly flushed using a
dcbf
or
dcbst
instruction. Only modified cachelines are
written.
Write-Through Caching
In a
write-through
caching policy, both the data cache and system memory are updated by
a write hit. A write miss updates only system memory—a new cacheline is not allocated.
Write-through caching can simplify the work of maintaining coherency between the data
cache and system memory. See
Software Management of Cache Coherency
, for
more information.
Control of the data-cache write policy depends on the address-translation mode:
•
In real mode, the data-cache write-through register (DCWR) specifies the write policy
for each physical-memory region. See
Data-Cache Write-Through Register (DCWR)
, for more information.
•
In virtual mode, the storage-attribute fields in the page-translation entry (TLB entry)
specify the data-cache write policy for virtual-memory regions. See
, for more information.
The write policy is in effect only when a memory region is defined as cacheable. Otherwise,
it is ignored.
Data-Cache Allocation Control
Software can control data-cacheline allocation and data PLB-request size by using the core-
configuration register 0 (CCR0):
•
Load misses from cacheable memory can be prevented from allocating cachelines by
using the
load without allocate bit, CCR0[LWOA]. This can provide a performance
advantage if memory reads are infrequent and tend to access non-contiguous
addresses.
•
Loads from non-cacheable memory (and those that do not allocate cachelines, as
described above) can be programmed to generate eight-word PLB requests, or to
generate only the number of data requested by the CPU. This is controlled using the
load-word-as-line bit, CCR0[LWL]. If CCR0[LWL]=1, the DCU requests eight words.
Using an eight-word request size provides the fastest access to sequential non-
cacheable memory. The requested data remains in the data-cache fill buffer until one
of the following occur:
-
A subsequent load replaces the contents of the fill buffer.
-
A store to an address contained in the fill buffer occurs.
-
A
dcbi
or
dccci
instruction is executed that affects an address in the fill buffer.
-
A
sync
instruction is executed.
Note that if CCR0[LWL]=1 and the target non-cacheable region is also marked as
guarded (i.e., the G storage attribute is set to 1), the DCU will request only the data
requested by the CPU.
•
Store misses to cacheable memory can be prevented from allocating cachelines by
using the store without allocate bit, CCR0[SWOA]. Software can use this bit to
prevent a store miss to write-back memory from allocating a cacheline. Instead, the
store updates system memory as if a write-through caching policy were in effect.
Unlike write-through caching, store hits to write-back memory
do not
automatically
update system memory when this bit is set.
See
, for more information on these control bits.
Data-Cache Performance
In general, a data-cache hit completes in one cycle without stalling the processor. The DCU
can perform certain cache operations in parallel to improve performance. Combinations of
load and store operations—cacheline fills, cacheline flushes, and operations that hit in the
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