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400
March 2002 Release
1-800-255-7778
Virtex-II Pro™ Platform FPGA Documentation
Chapter 3:
User Programming Model
R
Mask Generation
The rotate instructions write their results into the destination register under the control of
a mask specified in the rotate-instruction encoding. The mask is used to write or insert a
partial result into the destination register.
Rotate masks are 32-bits long. Two instruction-opcode fields are used to specify the mask:
MB and ME. MB is a 5-bit field specifying the starting bit position of the mask and ME is a
5-bit field specifying the ending bit position of the mask. The mask consists of all 1’s from
MB to ME
inclusive
and all 0’s elsewhere. If MB > ME, the string of 1’s wraps around from
bit 31 to bit 0. In this case, 0’s are found from ME to MB
exclusive
. The generation of an all-
zero mask is not possible.
The function of the MASK(MB,ME) generator is summarized as:
if MB < ME then
mask[MB:ME]
=
1’s
mask[all remaining bits]
=
0’s
else
mask[MB:31]
=
ones
mask[0:ME]
=
ones
mask[all remaining bits]
=
0’s
shows the generated mask for both cases.
Rotate Left then AND-with-Mask Instructions
shows the PowerPC
rotate left then AND-with-mask
instructions. For each type of
instruction shown, the “Operation” column indicates the rotate operation performed. The
column also shows, on an instruction-by-instruction basis, whether the CR0 field is
updated.
Figure 3-23:
Rotate Mask Generation
UG011_15_033101
MB < ME
0
MB
ME
31
0 0 . . . 0
1 1 . . . 1
0 0 . . . 0
MB > ME
0
ME
MB
31
1 1 . . . 1
0 0 . . . 0
1 1 . . . 1
Table 3-36:
Rotate Left then AND-with-Mask Instructions
Mnemonic
Name
Operation
Operand
Syntax
Rotate Left then AND-with-Mask Immediate
Instructions
r
A is loaded with the masked result of left-rotating (
r
S) the number of
bits specified by SH. The mask is specified by operands MB and ME.
rlwinm
Rotate Left Word Immediate then
AND with Mask
CR0 is
not
updated.
r
A,
r
S,SH,MB,ME
rlwinm.
Rotate Left Word Immediate then
AND with Mask and Record
CR0 is updated to reflect the result.
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