Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 491
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
PPC405D5 Exceptions and Interrupts
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It is possible that some of the target registers are updated when a data-storage
exception or an alignment exception occurs. When the instruction is restarted, the
modified registers are updated again.
• Store-multiple and store-string instructions.
It is possible that some of the target bytes in memory are updated when a data-storage
exception or an alignment exception occurs. When the instruction is restarted, the
modified memory locations are updated again.
• Scalar load instructions that cross a word boundary.
It is possible that some memory bytes have been accessed (read) when a data-storage
exception or alignment exception occurs. However, no registers are updated.
• Scalar store instructions that cross a word boundary.
It is possible that some of the target bytes in memory are updated when a data-storage
exception or alignment exception occurs. If the instruction is an update form, the
update register is
not updated. When the instruction is restarted, the modified memory
locations are updated again.
In the above cases, memory protection is never violated by the partial execution of an
instruction. No other instruction updates software-visible state if an exception occurs part-
way through execution.
To prevent load and store instructions from being interrupted and restarted, only scalar
instructions (not string or multiple) should be used to reference memory. Also, one of the
following two rules must be followed:
• The memory operand must be aligned on the operand-size boundary (see Table 2-1,
page 353 ).
• The accessed memory location must be protected by the guarded storage attribute
(see
Guarded (G) , page 452 ).
If a properly-aligned scalar load or store is interrupted, a memory-access request does not
appear on the processor local bus (PLB). Conversely, the processor does not interrupt a
properly-aligned scalar load or store once its corresponding memory-access request
appears on the PLB. Thus, the guarded storage attribute is not required to prevent
interruption of properly-aligned loads and stores.
PPC405D5 Exceptions and Interrupts
Table 7-1 lists the exceptions supported by the PPC405D5. Included is the exception-vector
offset into the interrupt-handler table, the exception classification, and a brief description
of the cause. Gray-shaded rows indicate exceptions that are not supported by the
PPC405D5 but can occur on other implementations of the PowerPC 405 processor. Refer to
Interrupt Reference , page 502 , for a detailed description of each exception and its
resulting interrupt.
Table 7-1: Exceptions Supported by the PPC405D5
Exception
Vector
Offset
Classification Cause
Critical Input 0x0100 Critical Asynchronous Precise External critical-interrupt signal.
Machine Check 0x0200 Critical Asynchronous Imprecise External bus error.
Data Storage 0x0300 Noncritical Synchronous Precise Data-access violation.
Instruction Storage 0x0400 Noncritical Synchronous Precise Instruction-access violation.
External 0x0500 Noncritical Asynchronous Precise External noncritical-interrupt
signal.