Xilinx Virtex-II Pro PPC405, Руководство пользователя

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406 www.xilinx.com March 2002 Release
1-800-255-7778 Virtex-II Pro™ Platform FPGA Documentation
Chapter 3: User Programming Model
R
instruction loads the nearest representable value into the destination register. For the
various instruction forms, these results are:
• Signed arithmetic—if the result exceeds 2
31
−
1 (
>
0x7FFF_FFFF), the instruction loads
the destination register with 2
31
−
1.
• Signed arithmetic—if the result is less than
−
2
31
(
<
0x8000_0000), the instruction loads
the destination register with
−
2
31
.
• Unsigned arithmetic—if the result exceeds 2
32
−
1 (
>
0xFFFF_FFFF), the instruction
loads the destination register with 2
32
−
1.
Multiply-Accumulate Instructions
Multiply-Accumulate Cross-Halfword to Word Instructions
Table 3-40 shows the PPC405 integer multiply-accumulate cross-halfword to word instructions.
These instructions take the lower halfword of the first source operand ( r A[16:31]) and
multiply it with the upper halfword of the second source operand ( r B[0:15]), producing a
32-bit product. The product is signed or unsigned, depending on the instruction. This
product is added to the value in the destination register,
r
D, producing a 33-bit
intermediate result. Generally,
r
D is loaded with the lower-32 bits of the 33-bit
intermediate result. However, if the instruction performs saturating arithmetic and the
intermediate result overflows,
r
D is loaded with the nearest representable value (see
Modulo and Saturating Arithmetic
, above).
For each type of instruction shown in Table 3-40 , the “Operation” column indicates the
multiply-accumulate operation performed. The column also shows, on an instruction-by-
instruction basis, how the XER and CR registers are updated (if at all).
Table 3-40:
Multiply-Accumulate Cross-Halfword to Word Instructions
Mnemonic Name Operation
Operand
Syntax
Multiply-Accumulate Cross-Halfword to Word
Modulo Signed Instructions
r D is added to the signed product ( r A[16:31])
×
( r B[0:15]),
producing a 33-bit result. The low-32 bits of this result are stored in
r D.
macchw Multiply Accumulate Cross Halfword
to Word Modulo Signed
XER and CR0 are
not
updated.
r D, r A, r B
macchw. Multiply Accumulate Cross Halfword
to Word Modulo Signed and Record
CR0 is updated to reflect the result.
macchwo
Multiply Accumulate Cross Halfword
to Word Modulo Signed with
Overflow Enabled
XER[OV,SO] are updated to reflect the result.
macchwo.
Multiply Accumulate Cross Halfword
to Word Modulo Signed with
Overflow Enabled and Record
XER[OV,SO] and CR0 are updated to reflect the
result.