Xilinx Virtex-II Pro PPC405, Руководство пользователя

Страница: 225 / 562

March 2002 Release www.xilinx.com 533
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Timer-Event Interrupts
R
• Halt PIT decrementing by loading the PIT with 0. Alternatively, auto-reload mode can
be disabled by clearing TCR[ARE]
=
0. When the PIT reaches to 0, decrementing is
halted.
Fixed-Interval Timer Events
A fixed-interval timer (FIT) event occurs when a selected bit in the time-base lower register
(TBL) changes from 0 to 1. The FIT-period bit in the timer-control register (TCR[FP]) is used
to select the TBL bit controlling the FIT event, as shown in
Table 8-6 .
Software cannot prevent FIT events from occurring. This is because the time-base register
is always incrementing and a valid fixed interval is always specified by TCR[FP].
A FIT event causes a FIT interrupt when both of the following bits are set to 1:
• The FIT interrupt-enable bit in the timer-control register, TCR[FIE].
• The external-enable bit in the machine-state register, MSR[EE].
FIT events always set the FIT-interrupt status bit in the timer-status register (TSR[FIS]
=
1).
This happens whether or not FIT interrupts are enabled. If TSR[FIS]
=
1 and the FIT
interrupt is disabled, the interrupt is considered pending. A FIT interrupt occurs if the
status bit is set and the interrupt is enabled.
To disable FIT interrupts, software must clear TCR[FIE]
=
0. TSR[FIS] should be cleared to 0
to remove pending FIT interrupts.
Table 8-6: Fixed-Interval Timer-Event Periods
TCR[FP] Selected TBL Bit
Time-Base
Clock Period
FIT Period
(300 MHz Clock)
00 23 2
9
1.71
µ
sec
01 19 2
13
27.3
µ
sec
10 15 2
17
0.437 msec
11 11 2
21
6.99 msec