Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 605
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Alphabetical Instruction Listing
R
dcba
Data Cache Block Allocate
Description
An effective address (EA) is calculated by adding an index to a base address, which are
formed as follows:
• The contents of register r B are used as the index.
• If the r A field is 0, the base address is 0.
• If the r A field is not 0, the contents of register r A are used as the base address.
The operation of this instruction depends on the cachability and caching policy of EA as
follows:
• If EA is cached by the data cache and has a write-back caching policy, the value of all
bytes in the data cacheline referenced by EA become undefined. The data cacheline
remains valid.
• If EA is not cached but is cachable with a write-back caching policy, a corresponding
data cacheline is allocated and the value of the bytes in that line are undefined.
• If EA is cachable and has a write-through caching policy, a no-operation occurs. This
is true whether or not EA is cached by the data cache.
• If EA is not cachable, a no-operation occurs.
dcba provides a hint that a block of memory is either no longer needed, or will soon be
written. There is no need to retain the data in the memory block. Establishing a data
cacheline without reading from main memory can improve performance.
dcba establishes an address in the data cache without copying data from main memory.
Software must ensure that the established address does not represent an invalid main-
memory address. A subsequent operation could cause the processor to attempt a write of
the cacheline to the invalid main-memory address, possibly causing a machine-check
exception to occur.
Pseudocode
EA
←
(
r A|0) + ( r B)
Allocate data cacheline corresponding to EA
Registers Altered
• None.
dcba r A, r B
X Instruction Form
31 0 0 0 0 0 r A r B 758 0
0 6 1
1 1
6 2
1 3
1