Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 449
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
Accessing Memory
R
• Enforce in-order execution of I/O instruction—The eieio instruction forces load and store
memory-access ordering. The instruction acts as a barrier between all loads and stores
that precede it and those that follow it.
eieio can be used to ensure that a sequence of
load and store operations to an I/O-device control register are performed in the
desired order.
• Synchronize instruction—The
sync
instruction guarantees that all preceding coherent
memory accesses initiated by a program appear to complete before the
sync
instruction completes. No subsequent instructions appear to execute until after the
sync
instruction completes.
On processors that support hardware-enforced shared-memory coherency, the sync
instruction also provides synchronization between devices that access memory. The
PPC405 does not provide hardware-enforced shared-memory coherency support. On
the PPC405, the
sync instruction is implemented identically to eieio .
In systems supporting hardware-enforced shared-memory coherency, sync can take
significantly longer to execute than eieio . Programmers should avoid using sync when
eieio performs the required ordering.
Preventing Inappropriate Speculative Accesses
PowerPC processors can perform speculative memory accesses, either to fetch instructions
or to load data. A speculative access is any access not required by the sequential-execution
model. For example, fetching instructions beyond an unresolved conditional branch is
considered speculative. If the branch prediction is incorrect, the program (as executed)
never requires the speculatively fetched instructions from the mispredicted path.
Sometimes speculative accesses are inappropriate. For example, an attempt to fetch
instructions from addresses that do not contain instructions can cause a program to fail.
Speculatively reading data from a memory-mapped I/O device can cause undesirable
system behavior. Speculatively reading data from a peripheral status register that is
cleared automatically after a read can cause unintentional loss of status information.
The PPC405 does not perform speculative data loads, but can speculatively fetch
instructions. Branch prediction can cause speculative fetching of up to five cacheable
instructions, or two non-cacheable instructions. If a
bctr or blr instruction is predicted as
taken, speculative fetching down the predicted path does not begin until all updates of the
CTR or LR ahead of the predicted branch are complete. This prevents speculative accesses
from unrelated addresses residing temporarily in the CTR and LR.
Using Guarded Storage
Speculative accesses can be prevented by assigning the guarded storage attribute (G) to
memory locations (see
Guarded (G) , page 452 ). An access to a guarded memory location is
not performed until that access is required by the sequential-execution model and is no
longer speculative. There is a considerable performance penalty associated with accessing
guarded memory locations, so the guarded storage attribute should be used only when
required.
Guarded storage can be specified in two ways, depending on the address-translation
mode:
• In real mode (MSR[IR]
=
0), the storage-guarded register (SGR) controls assignment of
the guarded attribute to memory locations.
• In virtual mode (MSR[IR]
=
1), the page-translation look-aside buffer (TLB) for a
virtual-memory page contains a G field that controls assignment of the guarded
attribute to memory locations.
Marking a memory location as guarded does not completely prevent speculative accesses
from that memory location. Speculative accesses from guarded storage can occur in the
following cases: